Analysis of higher order pitch division for sub-32nm lithography

The three knobs of optical lithography, namely process factor k1, wavelength (λ) and numerical aperture (NA) have been constantly pushed to print smaller features. To get an equivalent k1 value below the fundamental limit of 0.25, double patterning (DP) has recently emerged as a viable solution for the 32nm lithography node. Various DP techniques exist such as litho-etch-litho-etch (LELE), litho-freeze-litho-freeze (LFLF) and self-aligned sidewall spacer. In this paper, the potential of higher order pitch division (pitch/N, N>2) for sub-32nm lithography is analyzed. Compared to double patterning, higher order pitch division lithography offers higher resolution but also faces significant challenges such as added cost and tighter process control. Several process schemes are proposed and compared in terms of complexity, susceptibility to alignment error and CD uniformity control. It is shown that the overlay budget does not necessarily decrease compared to double patterning. The main challenge in higher order pitch division comes from controlling the key processing steps that directly form lines or spaces. In addition, line CD control is easier than space (gap) control in all four “positive-tone” processes studied, similar to the double patterning case. Among the proposed processes, a freezing assisted double spacer (FADS) process that is simpler than the common sidewall spacer approach shows promise for balanced process control.